Thin membranes of single crystal silicon are useful in a wide variety of applications. Some such applications include masks for X-ray lithographic exposures or integrated circuits, shadow or channeling masks for particle beams (such as ions or electrons), windows for atmospheric isolation, deformable optical and mechanical elements, sensors and transducers, and substrates for the fabrication of semiconductor devices.
Silicon wafers are conventionally produced by slicing thin discs of material from monocrystalline ingots. The discs are then thinned and polished using well known chem-mechanical grinding and polishing techniques. Wafers are commercially available in thicknesses ranging from 0.003 inches and up, with typical thicknesses being 0.015-0.025 inches. Below 0.003 inches in thickness, the chem-mechanical thinning techniques do not yield good results, and alternative chemical etching techniques are applied. Typically, the entire wafer is not thinned down since the result would be too fragile to handle. Instead, only portions of the wafer are thinned. The portions of the wafer which are not to be thinned are covered with an inert masking layer which protects such portions from the etching solution. The resultant structures, formed from chemically thinned silicon wafers, are referred to as membranes to distinguish them from the starting wafer material. These membranes are useful for applications that require thicknesses of silicon below that which can be achieved by chem-mechanical polishing, i.e. below approximately 0.003 inches.
The simplest procedure for forming a membrane from a silicon wafer is by a time down etching technique. In this process, the wafer is first covered with a masking layer on those portions of the wafer where etching is not desired. The wafer is then immersed in the etching solution, which begins to remove silicon from the unmasked areas. If the etch rate of the silicon in the solution being used is known, and if the etch rate is uniform over all areas of the wafer being etched, then the wafer can simply be immersed in the solution for the amount of time appropriate to reduce the wafer thickness to whatever is desired. The main drawbacks to this technique are that precise control of the etch rate and maintenance of high uniformity are difficult to achieve.
To solve the control problems associated with the time down approach, a variety of etch-stop techniques have been developed. The most commonly used technique is the p++ etch-stop. This technique relies on the fact that the etch rate of silicon in alkaline solutions drops substantially when the doping level of boron exceeds about 5.times.10.sup.19 per cm.sup.3. This technique has been described in U.S. Pat. No. 4,256,532 issued to Magdo, et al and in U.S. Pat. No. 4,589,952 issued to Behringer, et al. Use of this technique to create masks suitable for use with masked ion beam lithography is described by G. M. Atkinson, et al, "A Minimum Step Fabrication Process for the All-Silicon Channeling Mask, " Journal of Vacuum Science Technology, January/February 1987, pp. 219-222.
To form a membrane by the p++ etch-stop technique, a boron doped layer is formed on one surface of the silicon wafer. The wafer is then etched down starting from the other side. When the etching solution reaches the interface defined by the boron doped layer, the etching effectively stops due to the drop in etching rate. The thickness of the resulting membrane is then determined by the thickness of the boron doped layer. Since the maximum solubility of boron in silicon is about 1.times.10.sup.20 per cm.sup.3, this means that the boron doping level of the completed membrane must be in the range of approximately 0.5-1.times.10.sup.20 per cm.sup.3. A similar technique for fabricating a membrane by preferentially etching n+ silicon is disclosed in U.S. Pat. No. 3,713,922 issued to Lepselter, et al.
An alternative etch-stop technique is the p/n electrochemical etch-stop (ECE). In this case, a p/n junction is formed in the silicon wafer. Several well-known techniques for doing this are diffusion, ion implantation and epitaxy. By the application of an appropriate electrical voltage to the wafer, the etching of the silicon can be made to stop at the interface defined by the p/n junction. The thickness of the membrane is then determined by the location of the p/n junction.
The ECE technique is generally described by H. A. Waggener, "Electrochemically Controlled Thinning of Silicon," The Bell System Technical Journal, March, 1970, pp. 473-475. Enhancements to the original technique as described by Waggener include the use of other alkaline etchants to replace KOH (see T. N. Jackson, et al, "An Electrochemical P-N Junction Etch-Stop for the Formation of Silicon Microstructures," IEEE Electron Device Letters, Vol. EDL-2, No. 2, February 1981, pp. 44-45 and M. Hirata, et al, "A Silicon Diaphragm Formation for Pressure Sensor by Anodic Oxidation Etch-Stop," IEEE Conference Proceedings of Transducers 1985, June 1985, pp 287-290), and the use of multi-electrode biassing schemes (see U.S. Pat. No. 4,664,762 issued to Hirata and B. Kloek, et al, "A Novel Four Electrode Electrochemical Etch-Stop Method for Silicon Membrane Formation," IEEE Conference Proceedings of Transducers 1987, June 1987, pp. 116-119). The ECE technique can be used to produce large area membranes with good uniformity and precise thickness control.
Stress control is of importance in many membrane applications. As an example, a membrane with high tensile stress is desirable for X-ray masks. This permits the membrane to be made as flat as possible and improves its resistance to distortion when metal absorber patterns are applied to one surface. For shadow masks, a membrane of low but non-zero tensile stress is optimum. This keeps the membrane flat and but minimizes any distortion when the stencil holes are created.
The response of a membrane to a differential pressure across its two surfaces is also affected by its stress level. This is of importance in the use of membranes as windows or in some sensor applications. The resistance of the membrane to breakage due to mechanical vibrations, shocks or forces is also influenced by stress levels. Semiconductor device performance is also often a function of stress levels in the silicon material. Therefore, the suitability of a membrane for use in a semiconductor device would also be influenced by the membrane stress.
Several studies have been done on the effect of dopants on the stress levels in silicon wafers (see M. Sasiki, et al, "A Study of Strain in Ion Implanted Silicon," Semiconductor Processing, ASTM STP 850, American Society for Testing and Materials, 1984, pp. 96-109; N. Sato, "X-Ray Measurement of Lattice Strain Induced by Impurity Diffusion," Journal of the Physial Society of Japan, Vol. 38, No. 1, Jan. 1975, pp. 202-207; and K. Yagi, et al, "Anomalous Diffusion of Phosphorus into Silicon," Japanese Journal of Applied Physics, Vol. 9, No. 3, March 1970, pp 246-254). These studies have been related to the effects of any stress on the properties of the diffusion or implanted layer. In these studies X-ray analysis of doped wafers was performed to measure lattice strain for various dopant types and concentrations. This shows that the amount of strain induced depends on the size of the dopant atom. Boron and phosphorus, which are smaller than silicon, add tensile strain. Arsenic, which is almost the same size as silicon, adds only a small compressive strain. Larger atoms such as antimony add compressive strain. The strain increases with increasing dopant concentration until a maximum limit is reached. At this point, dislocations are created. Any additional dopant added at this point just causes more dislocations to be formed, rather than increasing the stress further. The aforementioned studies relate only to the effect of stress in bulk wafers, and do not discuss the implications of this physical effect for membrane fabrication.